library verilog;
use verilog.vl_types.all;
entity rab_internal is
    port(
        clock           : in     vl_logic;
        scanstart_n     : in     vl_logic;
        reset           : in     vl_logic;
        regtclk         : out    vl_logic;
        tferclk         : out    vl_logic;
        adcclk          : out    vl_logic
    );
end rab_internal;
